Silicon on insulator structures (“SOI structures” which may also be referred to herein as “SOI wafers” or “SOI substrates”) generally include a handle wafer, a silicon layer (also characterized as a “device layer”), and a dielectric layer (such as an oxide layer) between the handle wafer and the silicon layer. Transistors built within the top silicon layer of SOI structures switch signals quickly compared to transistors built on bulk silicon wafers, run at lower voltages and are much less vulnerable to signal noise from background cosmic ray particles. Each transistor is isolated from its “neighbor” or nearby transistor by a complete layer of silicon dioxide. These transistors are generally immune to “latch-up” problems and can be spaced closer together than transistors built on bulk silicon wafers. Building circuits on SOI structures increases productivity by allowing for more compact circuit designs, yielding more chips per wafer.
SOI structures may be prepared from silicon wafers sliced from single crystal silicon ingots grown in accordance with the Czochralski method. In one method for preparing a SOI structure, a dielectric layer is deposited on a polished front surface of a donor wafer. Ions are implanted at a specified depth beneath the front surface of the donor wafer to form a cleave plane, which is generally perpendicular to the axis, in the donor wafer at the specified depth at which they were implanted. The front surface of the donor wafer is then bonded to a handle wafer and the two wafers are pressed to form a bonded wafer. A portion of the donor wafer is then cleaved along the cleave plane to remove a portion of the donor wafer leaving behind a thin silicon layer (i.e., the device layer) to form the SOI structure.
A lack of bonding or weak bonding between the dielectric layer and the handle wafer at the periphery of the bonded structure causes the dielectric layer and/or the silicon layer at the periphery to be removed during subsequent cleaving. This results in a SOI structure that has a silicon layer (and typically also a dielectric layer) with a smaller radius than the handle wafer. The peripheral region of the structure that does not include the silicon layer is not available for device fabrication and is also a potential source of particle contamination. This unusable peripheral region may have a width of at least 1 mm or even 1.5 mm or more in 200 mm wafers and may include at least about 2.5% of the SOI structure's surface area.
There is a need for methods for manufacturing SOI wafers that allow the silicon layer of the structure to extend further to the edge of the handle wafer.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.